Coheron Words

4096-bit wave-aware compute substrate.
Floats are atoms. Coherons are molecules. Context is a field.

Abstract

Coheron Words are 4096-bit structured packets that behave like coherent wave packets inside a CPU core. Each Coheron contains hundreds of tiny-precision lanes, supports wave-like propagation, temporal echo, and optional safety metadata (CRC, keys, timestamps).

Large language models (LLMs) treat context as a flat sequence of tokens. Coherons treat context as a field: a wave of meaning that can propagate forward and backward in time, with controllable precision and structure. We are not replacing floats or LLMs — we are giving them a new substrate to live in. LF12_Specification.pdf LF12 Specification and Coheron word specification

Why 4096 Bits?

4096 bits is the largest structure that still behaves like a single computational particle inside the CPU's inner universe:

A Coheron Word packs 340 LF12 lanes (12-bit custom floats) into ~4080 bits, leaving room for CRC/control. The CPU can keep the entire word hot and local, avoiding RAM trips, NUMA penalties, and page faults. Beyond this size, performance collapses under cache thrashing and memory bandwidth saturation.

Coherons are therefore architecturally resonant objects: big enough to be expressive, small enough to stay coherent. They are bandwidth-shaped building blocks for future context engines and indexing schemes.

Unified PoC Metrics

Single core, single process, unified C benchmark (float baseline vs Coheron Words):

Mode Description Throughput
Float scalar y = atten * (a*x + b) ~14339.0 Mops/s
Float AVX2 Same kernel, AVX2-optimized ~21530.3 Mops/s
Coheron LF12 baseline LF12 lanes, direct transform ~49860794 lanes/s, ~149.6 logical Mops/s
Coheron LF12 wave LUT + wave mixing + temporal echo ~17980015 lanes/s, ~53.9 logical Mops/s

Floats are fast atoms. Coherons are slower per atom, but they move fields at once. That is why they matter for context-heavy systems like LLMs and search engines.

What Is a Coheron Word?

A Coheron Word is a 4096-bit structured packet that contains:

340 LF12 lanes ~4080 bits of tiny floats CRC / control bits wave mixing temporal echo forward + backward influence precision lensing

A float array is a list. A Coheron Word is a field.

A float update is a point operation. A Coheron update is a wave operation.

A float has no memory of its past. A Coheron Word can carry lineage, attenuation, echo, and identity, and can be extended with CRC and rolling keys for forward security.

Q and A

ASCII Wave + Smiley

Think of a Coheron as a wave that smiles back at you. Below is a tiny ASCII animation rendered in JavaScript. When the wave is in tune, the smile curves up:

Loading wave...

Context Wave (Multiple Lanes)

LLMs see context as a sequence of tokens. Coherons see context as multiple lanes of interacting waves. The animation below shows several lanes rippling in parallel:

Loading context...

JSON + CPU Info

Live JSON from /usr/local/bin/coherene-json16022026:

CPU info (truncated):

processor: 0 vendor_id: AuthenticAMD cpu family: 23 model: 1 model name: AMD EPYC Processor (with IBPB) stepping: 2 microcode: 0x1000065 cpu MHz: 2595.124 cache size: 512 KB physical id: 0 siblings: 2 core id: 0 cpu cores: 1 apicid: 0 initial apicid: 0 fpu: yes fpu_exception: yes cpuid level: 13 wp: yes flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm rep_good nopl cpuid extd_apicid tsc_known_freq pni pclmulqdq ssse3 fma cx16 sse4_1 sse4_2 x2apic movbe popcnt aes xsave avx f16c rdrand hypervisor lahf_lm cmp_legacy cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw topoext ssbd ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 rdseed adx smap clflushopt sha_ni xsaveopt xsavec xgetbv1 arat bugs: fxsave_leak sysret_ss_attrs null_seg spectre_v1 spectre_v2 spec_store_bypass retbleed smt_rsb srso div0 ibpb_no_ret bogomips: 5190.24 TLB size: 1024 4K pages clflush size: 64 cache_alignment: 64 address sizes: 40 bits
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